The present invention relates to an electrolytic plating method for plating any suitable items at a constant current density. The present method is especially suitable for the so-called "bump" plating of semiconductor components.
In order to uniformly plate a large number of substances and to also control the thickness of the plating deposit of each substance, it has been proposed to carry out a plating, wherein the total current supply may be determined from the total surface area of the elements to be plated simultaneously. The total surface area is estimated from the number of elements to be plated together in a plating bath and from their configuration. For example, a plating treatment can be carried out by supplying a total electric current determined by the multiplication of an optimum plating current density under a desired plating condition, with the estimated total surface area of elements to be plated, by regulating the applied voltage and observing the total current indicated by an amperemeter. The total surface area may be estimated by multiplying the surface area of any one article to be plated with the total number of articles having the same configuration and which are to be plated simultaneously in the same bath. However, it is tedious and difficult to get the total surface area exactly if the configuration of each article is complicated and if the total number of articles in one bath is very large. Besides, with prior art devices it is difficult to exactly maintain the desired plating conditions. Hence, a uniform plating thickness has been difficult to achieve heretofore.
It is also known to treat semiconductor components of so-called Planar or Mesa type semiconductors having diffusion zones with metal on every diffusion zone, in a plating process to prepare said semiconductor zones for providing electrodes. The metallic plating treatment is intended to provide the respective semiconductor component with a hemispherical "bump" which may be easily used as an electrode means. Stated differently, the plating must be a so-called "bump" plating which may be utilized not only for the plating of the diffusion zone of a semiconductor component with metal, but also for the preparation of integrated circuit terminals. For example, in the manufacture of a Planar type diode, first windows are provided by a selective photo-etching technique on the surface of a base plate of an N-type semiconductor having a silicon dioxide covering layer. A P-type impurity is permitted to diffuse selectively through the windows to form P-type zones. In the next step, a metallic anode layer is applied which tightly contacts every P-type zone. Simultaneously, metallic cathode layers are applied to cover the back side of the base plate of N-type semiconductor material. Thereafter, a so-called silver plating is carried out at every window which is provided with the metallic anode layer. This is accomplished by dipping a plurality of N-type semiconductors into a plating bath containing an electrolytic solution and by connecting a direct electric current source with its positive pole to a silver electrode in the plating bath. The silver electrode contacts the metallic anode layers of the semiconductor components. The negative pole of the direct electric current source is connected to the metallic cathode layers of the semiconductor component, whereby the flow direction of the direct plating current is in the same direction as the normal flow direction through the semiconductor.
The just described so-called "bump" plating of semiconductor components has the disadvantage that the total plated surface area increases with the growth of the hemispherical bump configuration. Thus, it becomes substantially impossible to continue the plating process with an optimum current density if the plating is carried out with a constant voltage or if the plating is carried out with a constant total current without adjusting the actual current density per unit area to the increasing surface area being plated. As a result, it is virtually impossible to obtain a uniform plating which is strongly bonded to the supporting surface and it becomes inevitable that the plating current passes through areas which are not supposed to be plated outside the P-type diffusion zone or zones. Thus, it is possible that bare portions of the N-type base plate may be plated due to the existance of pin holes in the covering layer of silicon dioxide or the edge of the base plate may be plated. Further, the normal current through the window parts may result in various depositions of plating metal, also in these areas which are not desired to be plated. As a result, it is a serious disadvantage that short circuits may occur between the undesired plating depositions and the normal plating electrodes in the windows.
These undesirably plated areas also provide an unnecessary electrostatic capacity. Accordingly, it becomes very difficult to determine the total current necessary for maintaining optimal plating conditions by simply estimating the total surface area to be plated. As stated, the estimation becomes virtually impossible, due to the increase of the total surface area, not only by the gross of the plated electrodes of semispherical "bump" configuration, but also by the deposition of plating metal in unexpected and undesired areas.
In order to remove plating metal from the above mentioned pin holes in the insulation layer of the semiconductor component, it is also known to employ a so-called periodic reverse plating method which uses a commercial alternate current. By reversing the electric current repeatedly it becomes possible to eliminate the plating metal deposition from the pin holes and around the edge of the base plate because the plating metal in these areas is dissolved into the electrolytic solution by ionization. This is possible because the PN junction present in each window of the semiconductor component does not permit the passage of the reverse current, whereas other areas, such as the pin holes and the edge of the base plate permit the passage of the reverse current by the ionization of the plating metal accumulated during the preceding plating process. As a result, a series of periodically repeated cycles of plating and electrolysis may be used to prepare a thick plating having a hemispherical configuration. However, the plating will take place only on every area in register with a complete PN junction and having a sufficient definite rectifying ability. However, this prior art method is not suitable for plating practically any bare area, such as a pin hole which has no rectifying ability or in areas of an incomplete PN junction which do not have a normal rectifying ability.
The above described convention periodic reverse plating method does not permit the complete elimination of plating metal on surface areas which are not supposed to be plated. Moreover, it becomes very difficult to carry out the plating operation at an optimum current density since surface areas remain which cannot be taken into account. Another drawback of the periodic reverse plating method is seen in that it requires an uneconomically long period of time.